superscalar

listen to the pronunciation of superscalar
Английский Язык - Английский Язык
Implementing instruction-level parallelism within a single processor, thereby allowing faster throughput than would otherwise be possible at the same clock speed
modern chips have multiple pipes of execution [say, two floating-point execute, two load-and-store floating-point, three integer ALU, a floating-point complex operation, two integer load, one integer store, two MMX ]; three-way or three-issue superscalar means that three instructions may be dispatched, to different execution pipes, per cycle "Superscalar floating point" implies simply that there is more than one floating-point pipe
In a RISC CPU, the ability to execute more than one instruction per clock cycle, achieved by having multiple parallel execution units The MIPS R10000 CPU routinely achieves instruction rates of 1 5 to 2 times its clock rate It uses five, independent execution units, and is able to execute instructions out of order, so that it can complete some instructions while waiting for the memory operands of others to arrive See also speculative execution and software pipelining
A type of microprocessor design incorporating multiple functional units together with sufficient hardware complexity to allow units to function relatively autonomously This type of design provides opportunities for concurrent operations to take place during a single clock cycle
Hardware designs that makes possible the simultaneous processing of multiple instructions
A second generation RISC designed for an optimal balance between compiler and machine instructions
Of a computer processor, being able to schedule operations for side-by-side execution Typically, a superscalar processor can schedule an integer operation, a floating point operation and a memory operation for simultaneous execution in different pieces of hardware Superscalar chips also make heavy use of pipelining
Processors able to execute more than one microinstruction in the same clock cycle, usually through the use of multiple instruction pipelines Applications usually have to be optimized for superscalar architectures to achieve maximum benefit
superscalar architecture
design of a processor in a manner that allows it to perform more than one operation each cycle
superscalar
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