standart pil

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standard cell

A pre-designed integrated circuit module that implements a specific function The data required to use the cell as part of a more complex circuit are contained in a computer file that can be accessed by other CAD tools Standard cells are designed to be interconnected by simple abutment with other cells from the same cell library

ASIC design cells that are optimized by transistor sizing for speed and die area This transistor sizing requires standard cell ASICs to be unique for all process levels In contrasts gate array cells are built from identically-sized transistors but require customization only at the interconnect levels

a primary cell used as a standard of electro-motive force

A semi-custom VLSI design methodology where gates (ands, ors, xors, registers ) are taken from a standard library These are typically arranged into rows with routing occuring in between the rows In CS137a: Day 2 slides, on page 6 (slide 12), a typical standard-cell row is shown In CS137a: Day 13, page 5 shows a couple of standard-cell rows

This device differs from the gate array since each cell may be different and optimized for each "standard" function There are no standard layers to the device and each layer of the chip is a unique design

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stan·dart pil